1. Field of the Invention
The present invention relates to a solid-state image pickup device and an image pickup device, which include a plurality of electrically-coupled substrates on which circuit elements constituting pixels are placed. Additionally, the present invention relates to a signal reading method of reading signals from pixels.
2. Description of the Related Art
Recently, demand for digital cameras as image input devices has been increasing with the rapid spread of personal computers. There are several factors determining the quality of digital cameras. One of the factors is the number of pixels of an image pickup element, which is an important factor for determining the resolution of a picked-up image. For this reason, digital cameras having more than 12,000,000 pixels have been commercialized recently.
As image pickup elements, amplified solid-state image pickup devices as typified by MOS image sensors such as CMOS (complementary metal oxide semiconductor), and charge coupled solid-state image pickup devices as typified by CCD (charge coupled device), are known. Those solid-state image pickup devices are widely used in digital still cameras, digital video cameras, and the like. Recently, as solid-state image pickup devices mounted on mobile devices such as cellular phones with cameras or PDA (personal digital assistants), MOS solid-state image pickup devices with low power voltage have been widely used in terms of power consumption or the like.
Regarding such MOS solid-state image pickup devices, various solid-state image pickup devices have conventionally been proposed, such as a solid-state image pickup device in which a semiconductor chip having a pixel region on which multiple pixels are arranged and a semiconductor chip on which a signal processing circuit is formed are electrically coupled to constitute one device. For example, Japanese Patent Laid-Open Publication No. 2006-49361 discloses a solid-state image pickup device including: a semiconductor chip on which micro pads are formed on a wiring layer side for each unit pixel cell or each cell including multiple pixels; and a signal processing chip on which micro pads are formed on a wiring layer side at positions corresponding to those of the micro pads on the semiconductor chip, the signal processing chip being coupled to the semiconductor chip through micro bumps.
FIG. 14 illustrates a configuration of a solid-state image pickup device of the related art. The solid-state image pickup device of the related art includes: a first substrate 201 having a MOS image sensor; and a second substrate 202 having a signal processing circuit, the first substrate 201 being placed over the second substrate 202. A light enters a surface of the first substrate 201 which opposes another surface thereof to be coupled to the second substrate 202. In other words, the first substrate 201 is configured to have a surface on which a wiring layer is formed, and another surface which opposes that surface with the wiring layer formed and which receives a light.
Multiple micro pads 203 are formed on the wiring layer of the first substrate 201, for each cell including unit pixels or for each cell including multiple pixels, as will be explained later. Additionally, multiple micro pads 204 corresponding to the micro pads 203 on the first substrate 201 are formed on a surface of the second substrate 202 on a wiring layer side. The first substrate 201 is placed over the second substrate 202 such that the micro pads 203 face the corresponding micro pads 204. The micro pads 203 and the micro pads 204 are electrically coupled via micro bumps 205 and thus integrated with one another. The micro pads 203 and 204 are formed so as to be smaller than normal pads.
The second substrate 202 is formed so as to be larger in area than the first substrate 201. Normal pads 206 are arranged on a surface of the second substrate 202, and are positioned outside the first substrate 101 in plan view. The pads 206 form an interface with a system other than the system including the two substrates.
FIG. 15 illustrates a configuration of the first substrate 201. The first substrate 201 includes: a pixel unit 208 on which multiple pixel cells 207 are two-dimensionally arranged; and a control circuit 209 that controls the pixel cells 207.
FIG. 16 illustrates a circuit configuration of the pixel cell 207 of the first substrate 201. Here, one pixel cell includes four pixels. The pixel cell 207 includes four photoelectric conversion elements 221A, 221B, 221C, and 221D. The photoelectric conversion elements 221A, 221B, 221C, and 221D are coupled respectively to sources of transfer transistors 222A, 222B, 222C, and 222D. Gates of the transfer transistors 222A, 222B, 222C, and 222D are coupled respectively to transfer wires 227A, 227B, 227C, and 227D supplied with transfer pulses. Drains of the transfer transistors 222A, 222B, 222C, and 222D are coupled commonly to a source of a reset transistor 223. A charge retention unit FD called floating diffusion is coupled to a gate of an amplifier transistor 224. The charge retention unit FD is positioned between the source of the reset transistor 223 and a drain of each of the transfer transistors 222A, 222B, 222C, and 222D.
A drain of the reset transistor 223 is coupled to a power wire 232. A gate of the reset transistor 223 is coupled to a reset wire 228 supplied with a reset pulse. A drain of an activating transistor 225 is coupled to the power wire 232. A source of the activating transistor 225 is coupled to a drain of the amplifier transistor 224. A gate of the activating transistor 225 is coupled to an activation wire 229 supplied with an activation pulse. A source of the amplifier transistor 224 is coupled to a drain of an injection transistor 230. A source of the injection transistor 230 is coupled to a ground potential. A gate of the injection transistor 230 is coupled to an injection wire 231 supplied with an injection pulse. The midpoint connecting the amplifier transistor 224 and the injection transistor 230 is coupled to an output terminal 226.
The photoelectric conversion elements 221A, 221B, 221C, and 221D are, for example, photodiodes. The photoelectric conversion elements 221A, 221B, 221C, and 221D generate signal charge based on the incident light and store the generated signal charge. The transfer transistors 222A, 222B, 222C, and 222D are transistors that transfer the signal charge charged in the photoelectric conversion elements 221A, 221B, 222C, and 221D to the charge retention unit FD. The transfer transistors 222A, 222B, 222C, and 222D are on/off controlled by transfer pulses supplied from the control circuit 209 via the transfer wires 227A, 227B, 227C, and 227D. The charge retention unit FD constitutes an input unit of the amplifier transistor 224. The charge retention unit FD is a floating diffusion capacitor that temporarily stores the signal charge transferred from the photoelectric conversion elements 221A, 221B, 221C, and 221D.
The reset transistor 223 is a transistor that resets the charge retention unit FD. The reset transistor 223 is on/off controlled by the reset pulse supplied from the control circuit 209 via the reset wire 228. It is also possible to reset the photoelectric conversion elements 221A, 221B, 221C, and 221D by simultaneously turning on the reset transistor 223 and the transfer transistors 222A, 222B, 222C, and 222D.
The amplifier transistor 224 is a transistor that amplifies a signal based on the signal charge stored in the charge retention unit FD and outputs the amplified signal from the source thereof. The activating transistor 225 and the injection transistor 230 are transistors that supply to the amplifier transistor 224, a current that drives the amplifier transistor 224. The activating transistor 225 is on/off controlled by an activation pulse supplied from the control circuit 209 via the activation wire 229. The injection transistor 230 is on/off controlled by an injection pulse supplied from the control circuit 209 via an injection wire 231.
The photoelectric conversion elements 221A, 221B, 221C, and 221D; the transfer transistors 222A, 222B, 222C, and 222D; the reset transistor 223; the amplifier transistor 224; the activating transistor 225; and the injection transistor 230 constitute the one pixel cell 207 including four pixels. In the case of the related art, a vertical signal line for outputting a signal to be read out of the substrate is not formed on the first substrate 201.
Hereinafter, operation of the pixel cell 207 is explained with reference to FIG. 17. Firstly, an injection pulse Pn1 is applied to the injection transistor 230 via the injection wire 231, thereby turning on the injection transistor 230. Thus, the voltage of the output terminal 226 is fixed to 0V. Then, a reset pulse Pr is applied to the reset transistor 223 via the reset wire 228, thereby turning on the reset transistor 223. Thus, the voltage of the charge retention unit FD is reset to high level (power voltage). When the voltage of the charge retention unit FD becomes high level, the amplifier transistor 224 turns on. Then, the application of the injection pulse Pn1 is released, thereby turning off the injection transistor 230. Then, an activation pulse Pk1 is applied to the activating transistor 225 via the activation wire 229, thereby turning on the activating transistor 225. As a result of the activating transistor 225 turning on, the voltage of the output terminal 226 increases up to the voltage corresponding to the voltage of the charge retention unit FD. The voltage of the output terminal 226 at that time is referred to as the reset level.
Then, the application of the activation pulse Pk1 is released, thereby turning off the activating transistor 225. Then, a transfer pulse Pt1 is applied to the transfer transistor 222A via the transfer wire 227A, thereby turning on the transfer transistor 222A. Thus, the signal charge of the corresponding photoelectric conversion element 221A is transferred to the charge retention unit FD. Then, an injection pulse Pn2 is applied to the injection transistor 230 via the injection wire 231, thereby turning on the injection transistor 230. Thus, the voltage of the output terminal 226 becomes 0V. Then, an activation pulse Pk2 is applied to the activating transistor 225 via the activation wire 229, thereby turning on the activating transistor 225. Thus, the voltage of the output terminal 226 increases up to the voltage corresponding to the voltage of the charge retention unit FD. The voltage of the output terminal 226 at that time is referred to as the signal level.
The signal based on the voltage of the output terminal 226 is input to the second substrate 202 via the micro bumps 205. The difference between the signal level and the reset level is detected in the second substrate 202, and a signal based on that difference is output from the solid-state image pickup device. Here, the explanation has been made with respect to the case where a signal is read from the photoelectric conversion element 221A which is one of the four photoelectric conversion elements 221A, 221B, 221C, and 221D. Similar operation is sequentially performed with respect to the other three photoelectric conversion elements 221B, 221C, and 221D.
By the above operation, exposing timings of the photoelectric conversion elements 221A, 221B, 221C, and 221D, which slightly differ thereamong, are substantially synchronized, thereby achieving synchronization of the upper and lower portions of the pixel unit 208. Therefore, it is possible to increase the image processing speed without causing image degradation at the time of reading signals.
The aforementioned related art is characterized in that the first substrate 201 having semi-manufactured pixels and the semi-manufactured second substrate 202 are used and mutually coupled by forming through holes or the like for coupling the two substrates, thereby completing the product. For this reason, neither the first substrate 201 having the semi-manufactured pixel, nor the semi-manufactured second substrate 202, cannot be products by themselves. For this reason, the related art is applicable for use to read signals using both the two substrates, but is not applicable for use to read signals using only one of the substrates. Specifically, in a case where a solid-state image pickup device compatible with multiple signal reading modes is configured, it is not possible to configure a solid-state image pickup device having both a function of reading signals using only one substrate by a predetermined reading mode and a function of reading signals using two substrates by another reading mode.